module cisfpga
			(
			 clock, resetn,
			 DATA_IN,
			 DIPSWn,

			 gRESET_PIXELn, gTXn,
			 S1, S2, S3, RESET_LOGICn,
			 RESET_ROWTKNn, ADV_ROWTKNn,
			
			 CLK_CISn,
			 ENA_CNT, WR, ADV_TKNn,
			 PCn, ENA_WL, DLn, ODD_SEL,
			
			 RAMP_LATCH, RAMP_DB,
			 POD_CLK, POD_DB
			);

input			clock, resetn;
input	[9:0]	DATA_IN;
input	[3:0]	DIPSWn;
output			gRESET_PIXELn, gTXn;
output			S1, S2, S3, RESET_LOGICn;
output			RESET_ROWTKNn, ADV_ROWTKNn;

output			CLK_CISn;
output			ENA_CNT, WR, ADV_TKNn;
output			PCn, ENA_WL, DLn, ODD_SEL;

output			RAMP_LATCH;
output	[13:0]	RAMP_DB;

output			POD_CLK;
output	[15:0]	POD_DB;

wire			zero;
wire			branch, decabnz;
wire			ioset, loadacc;
wire			swait;
wire			ramp, rsram, rlta;
wire			int_tmr;
wire			load_pc, cnten_pc, sclr_pc;
wire			load_opc, load_opr;
wire			load_acc, cntdn_acc, sclr_acc;
wire			load_cntref, cnten_tmr, sclr_tmr;
wire			init_porta, load_porta;
wire	[11:0]	INITA;
wire			init_portb, load_portb;
wire	[15:0]	INITB;
wire			sel_portb;
wire	[5:0]	PBADDR;
wire	[11:0]	PORTA;
wire	[15:0]	PORTB;

wire	[3:0]	rDIPSW;
wire			sclr_rampcnt, cnten_rampcnt;
wire			load_podreg;

/*
Definition of port A (PORTA) and port B (PORTB)
For MOD6FULLCHIP FPGA

Date		: APR-18-2004
Author		: Kunil Choe
CIS Module	: MOD6FULLCHIP

Port A (PORTA[11:0])
	PORTA[0]	<RESERVED>
	PORTA[1]	<RESERVED>
	PORTA[2]	<RESERVED>
	PORTA[3]	<RESERVED>
	PORTA[4]	RESET_LOGICn
	PORTA[5]	S3
	PORTA[6]	S2
	PORTA[7]	S1
	PORTA[8]	ADV_ROWTKNn
	PORTA[9]	RESET_ROWTKNn
	PORTA[10]	gTXn
	PORTA[11]	gRESET_PIXELn

Port B (PORTB[15:0])
	PORTB[0]	CLK_CISn
	PORTB[1]	<RESERVED>
	PORTB[2]	<RESERVED>
	PORTB[3]	ENA_CNT
	PORTB[4]	RAMP_LATCH
	PORTB[5]	WR
	PORTB[6]	ADV_TKNn
	PORTB[7]	PCn
	PORTB[8]	ENA_WL
	PORTB[9]	DLn
	PORTB[10]	ODD_SEL
	PORTB[11]	<RESERVED>
	PORTB[12]	sclr_rampcnt
	PORTB[13]	cnten_rampcnt
	PORTB[14]	load_podreg
	PORTB[15]	POD_CLK
*/

assign		RESET_LOGICn	= PORTA[4];
assign		S3				= PORTA[5];
assign		S2				= PORTA[6];
assign		S1				= PORTA[7];
assign		ADV_ROWTKNn		= PORTA[8];
assign		RESET_ROWTKNn	= PORTA[9];
assign		gTXn			= PORTA[10];
assign		gRESET_PIXELn	= PORTA[11];

assign		CLK_CISn        = PORTB[0];
assign		ENA_CNT         = PORTB[3];
assign		RAMP_LATCH      = PORTB[4];
assign		WR              = PORTB[5];
assign		ADV_TKNn        = PORTB[6];
assign		PCn             = PORTB[7];
assign		ENA_WL          = PORTB[8];
assign		DLn             = PORTB[9];
assign		ODD_SEL         = PORTB[10];

assign		sclr_rampcnt    = PORTB[12];
assign		cnten_rampcnt   = PORTB[13];
assign		load_podreg     = PORTB[14];
assign		POD_CLK         = PORTB[15];


assign		INITA			= 12'b1111_0001_0000;
assign		INITB			= 16'b0000_0110_1100_0111;

/*
module ctrlpath
		(
		clock, resetn,

		zero,
		
		branch, decabnz,
		ioset, loadacc,
		swait,
		ramp, rsram, rlta,

		int_tmr,
		rDIPSW,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_acc, cntdn_acc, sclr_acc,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, init_portb, load_portb,
		sel_portb, PBADDR
		);

*/
ctrlpath	CTRLPATH1	(.clock(clock), .resetn(resetn),

						 .zero(zero),

						 .branch(branch), .decabnz(decabnz),
						 .ioset(ioset), .loadacc(loadacc),
						 .swait(swait),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta),
						 .int_tmr(int_tmr),
						 .rDIPSW(rDIPSW),

						 .load_pc(load_pc), .cnten_pc(cnten_pc), .sclr_pc(sclr_pc),
						 .load_opc(load_opc), .load_opr(load_opr),
						 .load_acc(load_acc), .cntdn_acc(cntdn_acc), .sclr_acc(sclr_acc),
						 .load_cntref(load_cntref), .cnten_tmr(cnten_tmr), .sclr_tmr(sclr_tmr),
						 .init_porta(init_porta), .load_porta(load_porta),
						 .init_portb(init_portb), .load_portb(load_portb),
						 .sel_portb(sel_portb), .PBADDR(PBADDR));
/*
module datapath
		(
		clock, resetn,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_acc, cntdn_acc, sclr_acc,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, INITA,
		init_portb, load_portb, INITB,
		sel_portb, PBADDR,
		
		zero,
		
		branch, decabnz,
		ioset, loadacc,
		swait,
		ramp, rsram, rlta,
		int_tmr,
		
		PORTA, PORTB
		);

*/
datapath	DATAPATH1	(.clock(clock), .resetn(resetn),

						 .load_pc(load_pc), .cnten_pc(cnten_pc), .sclr_pc(sclr_pc),
						 .load_opc(load_opc), .load_opr(load_opr),
						 .load_acc(load_acc), .cntdn_acc(cntdn_acc), .sclr_acc(sclr_acc),
						 .load_cntref(load_cntref), .cnten_tmr(cnten_tmr), .sclr_tmr(sclr_tmr),
						 .init_porta(init_porta), .load_porta(load_porta), .INITA(INITA),
						 .init_portb(init_portb), .load_portb(load_portb), .INITB(INITB),
						 .sel_portb(sel_portb), .PBADDR(PBADDR),
						
						 .zero(zero),

						 .branch(branch), .decabnz(decabnz),
						 .ioset(ioset), .loadacc(loadacc),
						 .swait(swait),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta),
						 .int_tmr(int_tmr),

						 .PORTA(PORTA), .PORTB(PORTB));

rampcnt		RAMPCNT1	(.clock(clock), .resetn(resetn),
						 .sclr(sclr_rampcnt), .cnten(cnten_rampcnt),
						 .Q(RAMP_DB));

podreg		PODREG1		(.clock(clock), .resetn(resetn), .load(load_podreg),
						 .DATA({1'b0, 1'b0, 4'b0, DATA_IN}),
						 .Q(POD_DB));

dipswreg	DIPSWREG1	(.clock(clock), .resetn(resetn),
						 .DATAn(DIPSWn), .Q(rDIPSW));
endmodule
